What does Simutest do?
Simutest was founded in 1987 to provide innovative ATE test automation solutions for semiconductor designers and production test developers.
About Verifier (select question from given dropdown)
The Verifier vector translator is a comprehensive and full featured automatic test program development tool. It continues to be the latest in the test automation technology and efficiently meets the challenges associated with converting simulation / ATPG test vectors into various tester formats. The Verifier addresses both time to market as well as improved design to manufacturing productivity. It includes features that allow design and test engineers to collaborate, quickly generate and verify ATE test programs for more than 70 models from most major ATE systems including those from Advantest, Agilent, Teradyne, LTX, and NEXTEST.
Designers using the unique “playback mode” capability can seamlessly integrate Verifier into their design flow and verify that the converted ATE vectors can be reverified in the original design environment to significantly reduce post-silicon debug time.
Design, verification and test engineers can all use Verifier. The program is useful for anyone who is involved in the generation or analysis of test vectors.
WaveTools provides the most comprehensive simulator and tester support in the market. Over 30 different simulators and more than 70 testers are supported.
Verifier supports many different formats generated by CAE systems. It also supports various foundry specific formats. Supported Simulation / ATPG systems
Verifier supports more than 70 models of test systems from major vendors such as Agilent, Teradyne, LTX, NEXTEST, Credence, Schlumberger … For complete list, view Supported Test Systems.
Solaris (2.6 and above)
Linux (Kernel 2.4 and above)
Yes, Verifier extracts repeats, loops and subroutines from simulation/ATPG test vectors.
Yes, Verifier ATE reader module reads back generated ATE vectors and utilize them as test bench via a PLI playback interface to Verilog simulators that compares expected Vs. ATE vectors.
During design verification, you can use the Rule Analyzer to check datasheet timings and to ensure that your file will be compatible with your company's test methodology. The Rule Analyzer should also be used prior to translation to make sure that your simulation file will meet target tester constraints.
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